

Dergi
Glsvlsi 2026 Proceedings of the Great Lakes Symposium on VLSI 2026
Cilt
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ISSN
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Yayın Tarihi
22 Haziran 2026
In recent years, the definition of security in a locked design has been reformulated, and mechanisms that use cryptosystems and dense obfuscation techniques have been proposed. However, they increase the hardware complexity of a locked design significantly, restricting their application. In this paper, we present a novel logic locking technique using diffusion enabled by a matrix-vector multiplications (MVM) block, which can realize the multiplication of a variable vector first by a variable key matrix and second by a constant matrix in the integral domain and finite/Galois field. It takes advantage of the weakness of the well-known SAT-based attack and its variants, and the removal and structural analysis attacks by inserting an MVM block with a long chain of and and xor gates with key inputs into the original design and removing the traces of such an insertion through logic synthesis. It also uses optimization algorithms to reduce the number of adders/subtractors (xor) gates in the multiplication of a constant matrix by a variable vector in the integral domain (Galois field) and a key obfuscation technique to increase the security level. Experimental results show that the hardware complexity of locked circuits generated by the logic locking techniques using ciphers AES and Trivium is up to 17 × and 88 × larger than that of secure locked circuits generated by the proposed technique, respectively. It is also shown that these locked designs are resilient against the SAT-based attack and its variants, and they render existing removal and structural analysis attacks inefficient.